SILICON ENGINEERING

Emulation & Prototyping

SILICON ENGINEERING

Expertise in Emulation & Prototyping

FPGA Prototyping

  • FPGA based IP/SoC development
  • FPGA prototyping of ASIC designs
  • FPGA Design modification/optimization
  • Embedded C design
  • Architecture design, Hardware / software partitioning
  • FPGA Simulation/testbenches & Verification (UVVM, Cocotb, co-simulation)
  • Hardware/firmware verification and quality assurance
  • Synthesizable IP development and integration
  • RTL modeling & coding (VHDL and Verilog/SystemVerilog)
  • Concept & feasibility study
  • Micro Architecture Definition
  • Design Synthesis and Optimization
  • High-Speed Timing Closure
  • Post-synthesis simulation
  • FPGA debugging Hardware software co-verification

SoCs ASICS FPGA Validation

  • System Validation
  • Retargeting Services: FPGA-to-FPGA, ASIC-to-FPGA
  • System On Chip (Zynq, Zynq MPSoC)
  • Design for Xilinx, Altera/Intel and Lattice FPGAs
  • Interfacing with PCIe, DDR memories, high speed ADCs, Gigabit Ethernet

Post-Silicon Validation

  • Test plan development with features to be validated
  • Development of code in Embedded C, for all features to be validated
  • Development test cases Stimulus generation and response verification for regression testing and stress testing
  • Stimulus generation & response verification
  • Validation of Core blocks – CPU, GPU, VPU, DMAC, etc.
  • Validation of IO interfaces – USB, HDMI, SPI, I2C, CAN, Ethernet, etc.
  • Subsystem-level functional validation exercising multiple core & IO interfaces
  • Test case automation and regression
  • Debugging SoC issues
  • Power validation of silicon under varying low-power states
  • Power validation of subsystems under varying workload
  • Power characterization of blocks, interfaces & voltage domains
  • Electrical validation across PVT conditions and wafer lots
  • Custom test cases & standard benchmark
  • Performance analysis and validation
  • Real-time, at-speed multi-protocol subsystem and system-level test
  • Bare metal driver development for IO and core blocks & Board Bring-up
  • Bring up boards for silicon validation and wake-up