SILICON ENGINEERING

RISC-V & Processors

SILICON ENGINEERING

Expertise in RISC-V & Processors

RISC-V Core Design

  • Architecture design, Microarchitecture specification and implementation of In-order low power cores, & out-of-order RISC-V cores (RV32IMAFDC, RV64IMAFDC)
  • Custom logic architecture and design
  • RTL Design of all blocks & complete processor
  • Simulation test bench and test cases development
  • Synthesis, Static/Dynamic timing analysis
  • Area/timing/power convergence
  • Low-power design
  • High performance pipelines
  • Chip level integration
  • Performance modeling

RISC-V Core Verification

  • Developing verification strategy and planning for RISC-V (RV32IMAFDC, RV64IMAFDC)Core verification
  • Architecting RISC-V processor verification environments with supporting infrastructure and interfaces
  • Detailed unit-level & Processor level coverage-driven test plans creation including coverage metrics, debug modes and asynchronous events
  • Building constraint driven testbenches with drivers, monitors, scoreboards, checkers, sequences and sequencers
  • Development of test suites using Instruction Stream generators, including directed, random, and compliance tests
  • Reference Model development and integration to compare against RTL RISC-V core for test runs
  • Coverage creation and analysis permitting coverage driven verification
  • Assertion based verification
  • Enabling and managing regressions and triaging results
  • Scripting and Development for automation of testbench
  • RISC-V compliance testing & Formal Verification
  • Multi-Processor RISC-V Verification
  • Core Performance Analysis

RISC-V Test Suites

  • Arithmetic tests
  • Jump stress tests
  • Load store tests
  • Floating point tests
  • Loop tests
  • No fence tests
  • Illegal instructions tests
  • AMO tests
  • Single and Multi hart tests
  • Bit manipulations instruction tests
  • Unaligned load store tests
  • Full interrupt tests
  • EBREAK debug mode tests
  • MMU stress testing
  • Exception scenarios Tests
  • Compressed instruction Tests
  • Full privileged mode operation Tests
  • Performance verification suite
  • Security verification tests
  • Coverage model Tests

RISC-V Core Customization

  • RISC-V core custom instructions development & verification